s3c2440 nand flash 拷贝实验
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首先明确一下我们的编程步骤。
(1)、加电在nand_flash加载boot.s中4K以内的程序。这4k将自动拷贝到SRAM(片内RAM)执行。
(2)、我们需要用这4k的程序实现nand-flash中4K以后的程序的拷贝(当然,拷贝到SDRAM基址为0x30000000处)继续执行(main.o部分的程序)。对于SDRAM的初始化和Watchdog的禁用已经在前一个实验中使用到了,这里就不再详细叙述。主要来看一下nand-flash的初始化和使用。
查阅一下s3c2440的空间布局。查看手册图Figure 5-1. S3C2440A Memory Map after Reset一目了然。
有8个banks— Total 8 memory banksSix memory banks for ROM, SRAM, etc.Remaining two memory banks for ROM, SRAM, SDRAM, etc .
每个bank拥有128M空间。当访问bankx时,对应的地址范围是128*n 到 128*(1+n)tq2440使用了64M的nand flash和64M的SDROMNAND Flash不对应任何bank,他是通过几组寄存器来访问的;上电以后,nand flash开始的4k数据被自动的复制到芯片内部一个称为steppingstone的RAM上。steppingstore的映射地址为0,上面的4k完成初始化工作;SDRAM则使用bank6,起始位置为0x30000000
该实验中我们将使用SDRAM的bank6实验目的:
(1)、mem controller的原理和工作过程
(2)、bank的使用
(3)、nand flash的读写控制
(4)、启动代码流程分析
在实际编程中,uboot和vivi都是绝佳的参考源码,我这里参考的是vivi的代码。
vivi已经上传到新浪共享:http://ishare.iask.sina.com.cn/f/11353581.html
datasheet上关于启动原理的介绍:
Bank0:The data bus of BANK0 (nGCS0) should be configured with a width as one of 16-bit and 32-bit ones. Because theBANK0 works as the booting ROM bank (map to 0x0000_0000), the bus width of BANK0 should be determinedbefore the first ROM access, which will depend on the logic level of OM[1:0] at Reset.
下面小结一下对nand flash控制器的操作过程.
s3c2440对nandflash读写操作寄存器配置的流程:
s3c2440对nandflash读写操作寄存器配置的流程:
1.初始化
(1)NFCONT= (1<<0) //enable NAND flash controller
(2)NFCONT|= (1<<0)//chip disable
2.复位
(1)NFCONT&= ~(1<<1) //chip enable
(2)NFCMD= 0xff; //reset command
(3)while(!(NFSTAT& BUSY))等待NAND flashmemory ready to operate
3.读函数
(1)NFCONT&= ~(1<<1)//chip enable
(2)NFSTAT|= (1<<2) //NAND_CLEAR_RB ,RnBtransition is detected
(3)NFCMD= 0; //READ0,读上半叶
(4)//Write Address
NFADDR= i & 0xff;
NFADDR= (i >> 9) & 0xff;
NFADDR= (i >> 17) & 0xff;
NFADDR= (i >> 25) & 0xff;
(5)while(!(NFSTAT&(1<<0)) ); //NAND_DETECT_RB,等待NANDflash memory ready to operate
(6)*buf= (NFDATA & 0xff); //读数据线
(7)NFCONT|= (1<<1)//chip disable
用到的nand flash初始化读操作源码:
1 /*在第一次实用NAND Flash前,复位一下NAND Flash */
2 void nand_flash_reset()
3 {
4 NAND_CHIP_ENABLE;
5 NFCMD = 0xff; //reset command
6 wait_idle();
7 }
8
9 /*初始化NAND Flash */
10 void nand_flash_init()
11 {
12 //vivi init
13 int i = 0;
14 NFCONF = ( (7<<12)|(7<<8)|(7<<4)|(0<<0) );
15 NFCONT = ( (1<<4)|(0<<1)|(1<<0) );// Active low CE Control
16 NFSTAT = (0x6);//RnB Clear
17 NFCMD = 0xff; //reset command
18 for(i = 0; i < 10; i++)
19 ;
20 wait_idle();
21 /*
22 //----------------------------------------------------------------
23 // following is the copy module
24 //----------------------------------------------------------------
25 NFCONT |= 0x2;//@ Flash Memory Chip Disable
26 //----------------------------------------------------------------
27 @ Flash Memory Chip Disable
28 @ get read to call C functions (for nand_read())
29 @ copy vivi to RAM
30 ldr r0, =VIVI_RAM_BASE
31 mov r1, #0x0
32 mov r2, #0x20000
33 bl nand_read_ll
34 //---------------------------------------------------------------
35 */
36 /*
37 NFCONT = (1<<0);
38 NAND_CHIP_DISABLE;
39 nand_flash_reset();
40 */
41 }
42
43 #define BUSY 1
44 inline void wait_idle(void)
45 {
46 while(!(NFSTAT & BUSY));
47 NFSTAT |= BUSY;
48 }
49
50 #define NAND_SECTOR_SIZE 512
51 #define NAND_BLOCK_MASK (NAND_SECTOR_SIZE - 1)
52
53 /* low level nand read function */
54 int nand_flash_read(unsigned char *buf, unsigned long start_addr, int size)
55 {
56 int i, j;
57
58 if ((start_addr & NAND_BLOCK_MASK) || (size & NAND_BLOCK_MASK)) {
59 return -1; /* invalid alignment */
60 }
61
62 NAND_CHIP_ENABLE;
63
64 for(i=start_addr; i < (start_addr + size);) {
65 /*debug*/
66 (*(volatile unsigned long *)0x56000010) = 0x00015400;
67 (*(volatile unsigned long *)0x56000014) = 0x00000000;
68 /*debug*/
69 /* READ0 */
70 NAND_CLEAR_RB;
71 NFCMD = 0;
72
73 /* Write Address */
74 NFADDR = i & 0xff;
75 NFADDR = (i >> 9) & 0xff;
76 NFADDR = (i >> 17) & 0xff;
77 NFADDR = (i >> 25) & 0xff;
78
79 NAND_DETECT_RB;
80
81 for(j=0; j < NAND_SECTOR_SIZE; j++, i++) {
82 *buf = (NFDATA & 0xff);
83 buf++;
84 }
85 /*debug*/
86 if(i >= 512)
87 {
88 for(j = 0; j < 2048; j++)
89 ;
90 (*(volatile unsigned long *)0x56000014) &= (1 << 5) & (1 << 6);
91 for(j = 0; j < 2048; j++)
92 ;
93 }
94 /*debug*/
95 }
96 NAND_CHIP_DISABLE;
97 return 0;
98 }
在sram执行的启动汇编代码:
1 @----------------------------------------------------
2 @ boot.s
3 @ yeven @2010.20.28
4 @----------------------------------------------------
5 .text
6 .global _start
7 _start:
8 ldr sp,=4096
9 bl disable_wd @关闭看门狗
10 bl memsetup @初始化SDRAM
11 bl nand_flash_init @初始化nand-flash
12
13 @下面调用 nand_flash_read,它需要三个参数:目标地址,源地址,数据长度
14 ldr r0,=0x30000000 @SDRAM新的起始位置
15 mov r1,#4096 @main.o在nand-flash中的偏移,即数据起始位置
16 mov r2,#1024 @复制长度
17 bl nand_flash_read @调用vivi代码中的拷贝函数
18
19
20 bl led_on_s
21 ldr pc, = set_sp @设置堆栈,进入main.o执行
22 set_sp:
23 ldr sp,=0x34000000 @设置堆栈栈顶指针
24 ldr lr,=halt_loop @设置主函数返回地址
25 ldr pc,=main @执行主函数
26
27 halt_loop:
28 b halt_loop
29
30 led_on_s:
31 ldr r0,=0x56000010
32 mov r1,#0x00000400
33 str r1,[r0]
34 ldr r0,=0x56000014
35 mov r1,#0x00000000
36 str r1,[r0]
主函数执行代码,这一段将在sdram-0x30000000执行.他只是不停的闪灯:
1 /*
2 * mem-con.c yeven @2010.10.27
3 * learn to use the sdram,control the memory and memory map
4 * the main program locate at boot.s
5 * we just light the four leds to test the result.
6 */
7
8 //Register for the led
9 #define GPBCON (*(volatile unsigned long *)0x56000010)
10 #define GPBDAT (*(volatile unsigned long *)0x56000014)
11
12 //led-data register value(GPB5-GPB8)
13 #define LED0_ON (1 << (5*2))
14 #define LED1_ON (1 << (6*2))
15 #define LED2_ON (1 << (7*2))
16 #define LED3_ON (1 << (8*2))
17 #define GPB_ON(n) (~(1 << n))
18 #define GPB_OFF(n) (1 << n)
19
20 void delayms(unsigned int n)
21 {
22 int i = 0;
23 for(i = 0; i < 10240*n; i++)
24 ;
25 }
26
27 int main()
28 {
29 GPBCON |= (LED0_ON | LED1_ON | LED2_ON | LED3_ON); //led0-4
30 wh